PROGRESS: Completed Project	PROJECT REF: PA140
PROJECT TITLE: Three Dimensional Integrated Circuits
PROJECT DESCRIPTION: The invention is a simple method to fabricate multiple layers of transistors with one on top of each other in a 3D structure. Compare with some of the current practice, the new method is simple, flexible, controllable and capable to form much better performance transistors. The use of Metal-Induced Lateral Crystallization with special pattern of Metal placement results in much better control of the grain location, thus the transistors can be precisely placed on a single grain. In such, transistors with single crystal performance can be formed on polysilicon film with precise control. It solves the problem of poor performance of transistors formed on polysilicon film. Fabrication of transistors in 3D can lead to significant area saving and higher speed of operation, especially when compared with 2D technology. Unlike existing method to form 3D circuits, the new method provides flexibility to form not only 2 layers but also multiple layers. Also, the new invention does not require the use of special processing technology and is compatible with the current 2D technology. The invention can potentially provide a technological breakthrough in the mainstream IC technology to form the next generation high density, high performance 3D integration circuits. Also, it allows high performance transistors to be fabricated on top of any micro structure (such as MEMS). Potential Applications: - Static RAM (SRAM) - 3D Silicon-on-Insulator (SOI) CMOS - Micro-electro-mechanical systems (MEMS) Advantages over Present Technologies: 1. Simple and flexible way to fabricate transistors in a 3D manner 2. Area saving and higher speed of operation 3. Allow for multi-layers transistors 4. Allow for high performance transistors formed on polysilicon film 5. Compatible with current technology 6. Allow for fabricating high performance transistors on top of any micro structure (such as MEMS)
FOCUS AREA(S): Integrated Circuit Design
KEYWORDS: high-performance, data communication, telecommunication system, phase-locked-loop, frequency synthes
MODE OF COLLABORATION: Technology Licensing, Further R&D Collaboration
STATUS PATENT: Granted	PATENT NO: US6727517
ORGANIZATION: Hong Kong University of Science and Technology R and D Corporation Limited
CONTACT PERSON: Shirley Woo	EMAIL: cawoosw@ust.hk
TEL: (852)-23587918	FAX: (852)-23582751
WEBSITE: http://rdc.ust.hk/	DATE: 03/01/2005